LeadSoC Advantage in Embedded & Platform SW development

High speed access Technology (including emerging 5G) promises a paradigm change for multiple markets like Automotive, Telecom, IOT, Healthcare.
Virtualization and Containerization of functions is enabling faster development & deployment of these technologies
This calls for some functions implemented in Hardware to now have alternate Software Implementations
This in-turn drives a need for strong Embedded, DSP and RTOS Platform capabilities with domain exposure
LeadSoC is equipped to address all your DSP, embedded and Platform SW Design Requirements
Our in-house Embedded Labs, powered by rich open-source tool chain enabled sandboxes, enable our engineers to play & learn.

Flavors of Embedded Software Development

Boot ROM code design & optimization
Support for various boot modes; Secure boot support for ARM and x86 platforms ( UEFI ), Secure firmware upgrade
Board / OS bring-up for Multimedia gateway, Femto cell, Mobile devices & handhelds
BareMetal & Linux drivers for diverse set of interfaces ( Low sped / high speed / DSP )
Diagnostics framework for BNG router
Manufacturing diagnostics support for increasing factory yield, Field Mode escape analysis ( FMEA )
Post Silicon verification framework development & testing for ARM M0 and M4 Micro controller-based board

API provides a high-level programming interface to features supported by voice processor
Designed to work on multiple operating systems (mainly VxWorks & Linux). It has OS abstraction and Hardware abstraction layers
Works in two modes : External host mode where host processor is outside voice processor,
Internal host mode where OS & API runs in one of the Network processors
Designed to run in blocking , non-blocking & pseudo non-blocking modes, runs in multi-threaded environment, resource protection using semaphore
Enables configuration of SOC, statistics related to SOC runtime usage, has utilities to support debugging in case of runtime malfunction

Process-monitor for Femto Cell gateway to address process reinitialization & recovery
Tool for monitoring memory leaks in in Realtime
Runtime Utility to collect reboot reasons to enable analysis & fixing of crashes
Runtime utility to audit execution time of API’s, priority-based design fixes to optimize the execution time

L1 Layer covers PHY layer 3G, UMTS WCDMA, 2.5G Debugging PHY L1 blocks (FFT, modulator) on BTS & MS.
L2 Layer covers Porting MAC/Transport layer, message flows related to BCH/PDCCH, Control & Data channels framing, memory optimization
Bring up & verification of GiGe interface, HDLC encapsulation, EFM, Packet Classification engine Intel FlexRAN / DPDK
L3 Layer covers MPLS, OSPF, RIP, BGP, IPv4, IP VPN tunneling among other protocols

Fixed & Floating-point precision DSP software Design
MIPS & Memory optimized DSP implementation
Multicore, Multithreaded architecture
Application specific accelerators (FFT, Viterbi decoding)
DSP/BIOS , SmartDSPOS, FreeRTOS High Speed Interfaces to FPGA Serial Interfaces to ADCs

Domain coverage : Wireline PHY for Voice Media Gateway, DSL, Wireless PHY for 2G,3G,4G,5G-NR & Multimedia related to Speech & Audio codecs , Adaptive algorithms
coverage : TI DSPs, Starcore DSPs, CEVA DSP cores, Picochip DSP array & Multicore SoCs (DSP + ARM) : TI , Freescale, CEVA SoCs